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1 low power stereo audio codec features system ? high performance and low power multi - bit delta - sigma stereo adc and dac ? two independent i 2 s/pcm master or slave serial data port ? three pairs of analog input ? four pairs of analog output ? 2x0.9w stereo or 1.8w mono class d speaker driver ? ground centered headphone driver ? mono ear speaker driver ? 256 /384fs , u sb 12/ 24 mhz , f ractional pll for wide range of system clocks ? sophisticated analog input and output routing, mixing and gain ? support analog and digital microphone ? gpio ? i 2 c interface adc ? 24- bit, 8 to 96 khz sampling frequency ? 95 db dynamic range, 95 db signal to noise ratio, - 85 db thd+n ? low noise pre - amplifier ? auto level control (alc) and noise gate ? microphone bias dac ? 24- bit, 8 to 96 khz sampling frequency ? 95 db dynamic range, 95 db signal to noise ratio, - 85 db thd+n ? digital peak limiter (dpl) ? pop and click noise suppression dsp ? flexible digital signal routing and mixing ? asynchronous sample rate conversion ? six programmable digital filters for peq and noise reduction ? stereo enhancement ? suppo rt u/a law low power ? 1.8v to 3.3v operation ? 7 mw playback; 16 mw playback and record applications ? mid /pho blet ? smart phone ? digital amplifier o rdering i nformation es83 96 -40 c ~ +85 c qfn - 4 8 ES8396
everest semiconductor confidential ES8396 revision 5 . 0 2 march 2018 1. block diagram dcvdd dpvdd dgnd avdd avddldo agnd spkvdd1 spkvdd2 spkldo spkgnd adcvrp dacvrp vmid micbias cpvdd cpgnd cptop cpbot cpvssp mclk sda scl gpio2/dmic_scl2 gpio1/dmic_scl1 adcdat2 dacdat2 lrck2 bclk2 adcdat1 dacdat1 lrck1 bclk1 l/r dac out ainl/ainr monop/monon l/r line mixer out l/r aux mixer out l/r mono mixer out l/r line mixer out l/r aux mixer out l/r mono mixer out l/r hp mixer out l/r, p/n spk mixer out i 2 c gpio pll clock mgr mic bias line mixer aux mixer mono mixer hp mixer spk mixer charge pump line driver aux driver mono driver hp driver spk driver pga power supply and ldo l/r adc pga out d2s preamp i 2 s/pcm 2 i 2 s/pcm 1 dsp asrc mixing adc alc dac dpl programmable filters peq se u/a law stereo dac ainl/ainr monop/monon mic1p/mic1n mic2p/mic2n micp/micn lout1/rout1 (lout1n) monoutp/monoutn hplout/hprout spkloutp/spkloutn spkroutp/spkroutn stereo adc analog reference
everest semiconductor confidential ES8396 revision 5 . 0 3 march 2018 2. pin out and description name type description mclk di master clock sda dio i 2 c data scl di i 2 c clock gpio1 dio gpio (digital mic clock, adc lrck, etc) gpio2 dio gpio (digital mic clock, adc lrck, etc) adcdat 1/ad0 dio i 2 s/pcm serial data out; also used as i 2 c address dacdat 1 di i 2 s/pcm serial data in lrck 1 dio i 2 s/pcm left and right clock bclk 1 dio i 2 s/pcm bit clock adcdat 2 dio i 2 s/pcm serial data out dacdat 2 di i 2 s/pcm serial data in lrck 2 dio i 2 s/pcm left and right clock bclk 2 dio i 2 s/pcm bit clock ain l/jd1 ai left analog line input or jack detect 1 ain r/jd2 ai right analog line input or jack detect 2 mono p ai mono positive input or left analog line input mono n ai mono negative input or right analog line input micp ai mic positive input or left analog line input micn /dmic_sda ai mic negative input or right analog line input or digital mic data ES8396 qfn 48 gpio1 dacdat1 adcdat1 bclk1 lrck1 sda scl dpvdd dgnd dcvdd mclk gpio2 1 2 3 4 5 6 7 8 9 10 11 12 micp ainl ainr monon monop micbias lout rout adcdat2 dacdat2 lrck2 bclk2 24 23 22 21 20 19 18 17 16 15 14 13 cpvssp cptop cpvdd dacvrp monoutn monoutp avddldo avdd agnd vmid adcvrp micn 36 35 34 33 32 31 30 29 28 27 26 25 cpgnd cpbot hprout hplout spkldo spkgnd spkloutp spkvdd1 spkloutn spkroutn spkvdd2 spkroutp 37 38 39 40 41 42 43 44 45 46 47 48
everest semiconductor confidential ES8396 revision 5 . 0 4 march 2018 lout ao left line out rout/loutn ao right line out or negative left line out monout p ao mono positive output monout n ao mono negative output hp lout ao left headphone out hp rout ao right h eadphone out sp kloutp ao positive left speaker out sp kloutn ao negative left speaker out sp kroutp ao positive right speaker out sp kroutn ao negative right speaker out cpvdd charge pump power supply cpgnd charge pump ground cptop charge pump capacitor top cpbot charge pump capacitor bottom cp vssp charge pump filtering micbias ao mic bias adcvrp adc reference filtering dacvrp dac reference filtering vmid common mode filtering dcvdd digital core power supply d p vdd digital io power supply dgnd digital ground avdd analog power supply avddldo analog ldo power supply agnd analog ground spkvdd1 speaker driver power supply spkvdd2 speaker driver power supply spkldo speaker driver ldo power supply spk gnd speaker driver ground
everest semiconductor confidential ES8396 revision 5 . 0 5 march 2018 3. typical application circuit mcl k i2s1_dacdat i2s1_adcdat i2s1_lrck i2s1_alrck_gpio i2s1_bclk i2c_scl i2c_sda mou t _ p mou t _ n hp_l hp_r sp kl _ p sp kl _ n sp kr_ p sp kr_ n va_dut(+3.3v) vcp_dut(+1.8v) vspk_dut(+2.5v - 4.3v) vd_dut(+1.8v - +3.3v) vp_dut(+1.8v - +3.3v) 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 10uf 10uf 10uf 0.1uf 0.1uf agnd agnd agnd spk_gnd agnd agnd 0.1uf 4.7uf agnd agnd agnd dgnd dgnd 0.1uf i 2 ca 0 0 1 1 mi cp mi cn micbias mon o i n_ p mon o i n_ n a i n_ l a i n_ r lout_p rou t _ n adclrck/gpio 1 dacdat1 2 adcdat1 3 bclk1 4 l r ck 1 5 sda 6 scl 7 dpvdd 8 dgnd 9 dcvdd 10 mcl k 11 adclrck2/gpio 12 b cl k 2 13 l rc k 2 14 d acd at 2 15 a dcd at 2 16 rou t 17 l ou t 18 micbias 19 monop 20 monon 21 a inr 22 a inl 23 mi cp 24 mi cn 25 adcvrp 26 v mi d 27 agnd 28 avdd 29 avddldo 30 monooutp 31 monooutn 32 dacvrp 33 cp vd d 34 cp top 35 cp vssp 36 cpgn d 37 c p bo t 38 hprout 39 hplout 40 spkldo 41 spkgnd 42 spkl o ut p 43 spkv d d1 44 spkl o ut n 45 spkro ut n 46 spkv d d2 47 spkro ut p 48 t he rmal 49 ES8396 i2s2_dacdat i2s2_adcdat i2s2_lrck i2s2_alrck i2s2_sclk 10uf 0.1uf spk_gnd 0 10uf 0.1uf agnd 10k vp_dut i 2 ca 0 10k 10k vp_dut 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf microphone 2.2k 2.2k agnd 10k 10k agnd spk_gnd receiver earpiece 6 1 2 3 4 5 headphone agnd 10k hpdetect vp_dut 8 o hm rsp e a ke r 8ohm lspeaker spk_gnd agnd dgnd 33 33 0.01uf 0.01uf agnd
everest semiconductor confidential ES8396 revision 5 . 0 6 march 2018 4. clock modes and samp ling frequencies the device supports three types of clocking: standard audio clocks (256fs, 384fs, 512fs, etc), usb clocks (12/24 mhz), and an on - chip 22 - bit fractional pll clock. according to the serial audio data sampling frequency (fs) , the device can work in two speed modes : single speed mode or double speed mode. in single speed mode, fs normally ranges from 8 khz to 48 khz, and in double speed mode, fs normally range from 64 khz to 96 khz. the device can work either in master clock mode or slave clock mode. in slave mode, lrck an d sclk a re supplied externally, and lrck and sclk must be synchronously derived from the sy stem clock with specific rates. in master mode, lrck and sclk ar e derived internally from device master clock. 5. micro - controller configura tion interface the device supports s tandard i 2 c micro - controller configuration interface. external micro - controller can completely configure the device through writing to in ternal configuration registers. i 2 c interface is a bi - directional serial bus that uses a serial data line (sda) and a s erial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 1 . data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high wi th msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 100 k bps. figure 1 data transfer for i 2 c interface a master controller initiates the transmission by sending a start signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 00 10 00x, where x equals ad0 . the rw bit indicates the slave data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the commu nication by generating a stop signal, which is defined as a low -to - high transition at sda while scl is high.
everest semiconductor confidential ES8396 revision 5 . 0 7 march 2018 in i 2 c interface mode, the registers can be written and read. the formats of write and read instructions are shown in table 1 and table 2 . pl ease note that, to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. there are no acknowledge bit after data to be written or read, this is the only difference from the i 2 c protocol. table 1 write data to register in i 2 c interface mode chip address r/w register address data to be written 001000 ad0 0 ack ram ack data table 2 read data from register in i 2 c interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data 6. digital audio interf ace the device provides many formats of serial audio data interface to the input of the dac or out put from the adc through lrck, b c lk (sclk) and dacdat/adcdat pins. these formats are i 2 s, left justified, right justified, dsp/pcm and tdm mode. dac input dacdat is sampled by the device on the rising edge of sclk. adc data is out at adcdat on the falling edge of sclk. the relationship of sdata (dacdat/adcdat ), scl k and lrck with these formats are shown through figure 2 to figure 6 . n-2 n-1 n 3 2 1 1 n-2 n-1 n 3 2 1 1 figure 2 i 2 s serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 n-2 n-1 n 3 2 1 figure 3 left justified serial audio data format up to 24 - bit
everest semiconductor confidential ES8396 revision 5 . 0 8 march 2018 n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 4 right justified serial audio data format up to 24 - bit figure 5 dsp/pcm mode a figure 6 dsp/pcm mode b
everest semiconductor confidential ES8396 revision 5 . 0 9 march 2018 7. electrical character istics absolute maximum rat ings continuous operation at or beyond these conditions may permanently damage the device. parameter min max analog supply voltage level - 0.3v + 4 . 5 v digital supply voltage level - 0.3v +5.0v input voltage r ange dgnd - 0.3v dvdd+0.3v operating temperature range - 40 c +85 c storage temperature -65 c +150 c recommended operatin g conditions parameter min typ max unit analog supply voltage level 2.0 3.3 3.6 v analog supply voltage level C class d 2.5 4 .0 4 . 3 v digital supply voltage level C dcvdd 1.6 3.3 3.6 v digital supply vo ltage level C dpvdd (recommend to be the same as dcvdd) 1.6 3.3 3.6 v adc analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd= 3.3v, d cvdd= 1.8v, agnd=0v , dgnd=0v, ambient temperature= 25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit adc performance signal to noise ratio (a - weigh) 85 95 98 db thd+n - 88 - 85 - 75 db channel separation (1khz) 80 85 90 db interchannel gain mismatch 0.1 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 50 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level avdd/3.3 vrms input impedance 20 k
everest semiconductor confidential ES8396 revision 5 . 0 10 march 2018 dac analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd=3.3v, dcvdd=1.8v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit dac performance signal to noise ratio (a - weigh) 83 96 98 db thd+n -85 -83 -75 db channel separation (1khz) 80 85 90 db interchannel gain mismatch 0.05 db filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 40 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 40 db de - emphasis error at 1 khz (single speed mode only) fs = 32khz fs = 44.1khz fs = 48khz 0.002 0.013 0.0009 db analog output full scale output level avdd/3.3 vrms power consumption characteristics parameter min typ max unit normal operation mode dvdd=1.8v, avdd=1.8v: play back play back and record dvdd=3.3v, avdd=3.3v: play back play back and record 7 16 31 59 mw power down mode dvdd=1.8v, avdd=1.8v dvdd=3.3v, avdd=3.3v tbd tbd mw serial audio port sw itching specificatio ns parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz
everest semiconductor confidential ES8396 revision 5 . 0 11 march 2018 lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low tsclkl 15 ns sclk pulse width high tsclkh 15 ns sclk falling to lrck edge tslr C 10 10 ns sclk falling to sdout valid tsdo 0 ns sdin valid to sclk rising setup time tsdis 10 ns sclk rising to sdin hold time tsdih 10 ns figure 8 serial audio port timing i 2 c switching specificat ions parameter symbol min max unit scl clock frequency f scl 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us sda hold time from scl falling t twdh 900 ns sda setup time to scl rising t twds 100 ns rise time of scl t twr 300 ns fall time scl t twf 300 ns
everest semiconductor confidential ES8396 revision 5 . 0 12 march 2018 s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 i 2 c timing
everest semiconductor confidential ES8396 revision 5 . 0 13 march 2018 8. package 9. corpo rate information everest semiconductor co., ltd. ????? 1355 ???? , ? 215021 email: info@everest - semi.com

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